1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to structures and manufacturing methods for forming through-silicon vias.
2. Description of the Related Art
In recent years, the device features of modern, ultra-high density integrated circuits have been steadily decreasing in size in an effort to enhance the overall speed, performance, and functionality of the circuit. As a result, the semiconductor industry has experience tremendous growth due to the significant and ongoing improvements in integration density of a variety of electronic components, such as transistors, capacitors, diodes, and the like. These improvements have primarily come about due to a persistent and successful effort to reduce the critical dimension—i.e., minimum feature size—of components, directly resulting in the ability of process designers to integrate more and more components into a given area of a semiconductor chip.
Improvements in integrated circuit design have been essentially two-dimensional (2D)—that is, the improvements have been related primarily to the layout of the circuit on the surface of a semiconductor chip. However, as device features are being aggressively scaled, and more semiconductor components are being fit onto the surface of a single chip, the required number of electrical interconnects necessary for circuit functionality dramatically increases, resulting in an overall circuit layout that is increasingly becoming more complex and more densely packed. Furthermore, even though improvements in photolithography processes have yielded significant increases in the integration densities of 2D circuit designs, simple reduction in feature size is rapidly approaching the limit of what can presently be achieved in only two dimensions.
As the number of electronic devices on single chip rapidly increases, three-dimensional (3D) integrated circuit layouts, or stacked chip design, have been utilized for some semiconductor devices in an effort to overcome some of the feature size and density limitations associated with 2D layouts. Typically, in a 3D integrated circuit design, two or more semiconductor dies are bonded together, and electrical connections are formed between each die. One method of facilitating the chip-to-chip electrical connections is by use of so-called through-silicon vias, or TSV's. A TSV is a vertical electrical connection that passes completely through a silicon wafer or die, allowing for more simplified interconnection of vertically aligned electronic devices, thereby significantly reducing integrated circuit layout complexity as well as the overall dimensions of a multi-chip circuit. Some of the benefits associated with the interconnect technology enabled by 3D integrated circuit designs include accelerated data exchange, reduced power consumption, and much higher input/output voltage densities.
Through-silicon vias can be integrated into virtually any phase of semiconductor device manufacturing, including via-first, via-middle, and via-last schemes. Currently, most integration development has tended to focus on forming TSV's within an active area of the semiconductor die—e.g., via-middle and via-last schemes. A typical prior art process for forming TSV's based on a via-middle scheme, wherein the TSV's are formed after transistor and contact element formation, is illustrated in FIGS. 1a-1f, and will now be discussed in detail below.
FIG. 1a is a schematic cross-sectional view depicting one stage in a via-middle integration scheme used in the formation of a TSV in accordance with an illustrative prior art process. As shown in FIG. 1a, a semiconductor chip or wafer 100 may comprise a substrate 101, which may represent any appropriate carrier material above which may be formed a semiconductor layer 102. Additionally, a plurality of schematically depicted active and/or passive circuit elements 103, such as transistors, capacitors, resistors and the like, may be formed in and above the semiconductor layer 102, in which case the semiconductor layer 102 may also be referred to as a device layer 102. Depending on the overall design strategy of the wafer 100, the substrate 101 may in some embodiments be comprised of a substantially crystalline substrate material (i.e., bulk silicon), whereas in other embodiments the substrate 101 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer 101a may be provided below the device layer 102. It should be appreciated that the semiconductor/device layer 102, even if comprising a substantially silicon-based material layer, may include other semiconducting materials, such as germanium, carbon and the like, in addition to appropriate dopant species for establishing the requisite active region conductivity type for the circuit elements 103.
FIG. 1a also illustrates a contact structure layer 104, which may be formed above the device layer 102 so as to provide electrical interconnects between the circuit elements 103 and a metallization system (not shown) to be formed above the device layer 102 during subsequent processing steps. For example, one or more interlayer dielectric (ILD) layers 104a may be formed above the device layer 102 so as to electrically isolate the respective circuit elements 103. The ILD layer 104a may comprise, for example, silicon dioxide, silicon nitride, silicon oxynitride, and the like, or a combination of these commonly used dielectric materials. Furthermore, depending on the device design and overall process flow requirements, the interlayer dielectric layer 104a may also comprise suitably selected low-k dielectric materials, such as porous silicon dioxide, organosilicates, organic polyimides, and the like. Thereafter, the ILD layer 104a may be patterned to form a plurality of via openings, each of which may be filled with a suitable conductive material such as tungsten, copper, nickel, silver, cobalt and the like (as well as alloys thereof), thereby forming contact vias 105. Additionally, in some embodiments, one or more trench openings may also be formed in the ILD layer 104a above one or more of the vias openings noted above. Thereafter, depending on the specified processing parameters, any trenches formed in the ILD layer 104a may be filled in a common deposition step with a similar conductive material such as noted for the contact vias 105 above, thereby forming conductive lines 106 as may be required by the device requirements.
As shown in FIG. 1a, in certain embodiments, a hardmask layer 107, which may act as a stop layer for a subsequently performed chemical-mechanical polishing (CMP) process, may thereafter be formed above the contact structure layer 104. The hardmask layer 107 may comprise a dielectric material having an etch selectivity relative to at least the material comprising the upper surface portion of the ILD layer 104a, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN) and the like. In some illustrative embodiments, the hardmask layer 107 may be formed above the contact structure layer 104 by performing a suitable deposition processes based on parameters well known in the art, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, atomic layer deposition (ALD), spin on coating, and the like. Thereafter, a patterned resist mask layer 108 may be formed above the hardmask layer 107 based on typical photolithography processes, such as exposure, baking, developing, and the like, so as to provide openings 108a in the mask layer 108, thereby exposing the hardmask layer 107.
FIG. 1b shows the illustrative prior art process of FIG. 1a in a further manufacturing stage, wherein an etch process 109 is performed to create TSV openings 110 in the wafer 100. As shown in FIG. 1b, the patterned resist mask layer 108 may be used as an etch mask during the etch process 109 to form openings in the hardmask layer 107, and to expose the ILD layer 104a of the contact structure layer 104. Thereafter, the etch process 109 may be continued, and the patterned mask layer 108 and patterned hardmask layer 107 may be used as mask elements to form the TSV openings 110 through the contact structure layer 104, through the device layer 102, and into the substrate 101. In certain embodiments, the etch process 109 may be a substantially anisotropic etch process, such as a deep reactive ion etch (REI), and the like. Depending on the chip design considerations and etch parameters employed during the etch process 109, the sidewalls 110s of the TSV openings 110 may be substantially vertical with respect to the front and back surfaces 100f, 100b of the wafer 100 (as shown in FIG. 1b), whereas in some embodiments the sidewalls 110s may be slightly tapered, depending on the depth of the TSV openings 110 and the specific etch recipe used to perform the etch process 109. Moreover, since the TSV openings 110 may pass through and/or into a plurality of different material layers, such as the ILD layer 104a, the device layer 102, a buried insulation layer 101a (when used), and the substrate 101, the etch process 109 may be substantially non-selective with respect to material type, such that a single etch recipe may be used throughout the duration of the etch In other illustrative embodiments, however, the etch process 109 may comprise a plurality of different etch recipes, each of which may be substantially selective to the material layer being etched.
Depending on the overall processing and chip design parameters, the openings 110 may have a width dimension 110w ranging from 1-10 μm, a depth dimension 110d ranging from 5-50 μm or even more, and an aspect ratio—i.e., depth-to-width ratio—ranging between 4 and 25. In one embodiment, the width dimension 110w may be approximately 5 μm, the depth dimension 110d may be approximately 50 μm, and the aspect ratio may be approximately 10. Typically, however, and as shown in FIG. 1b, the TSV openings 110 do not, at this stage of fabrication, extend through the full thickness of the substrate 101, but instead stop short of the back surface 100b of the wafer 100. For example, in some embodiments, the etch process 109 is continued until the bottom surfaces 110b of the TSV openings 110 come within a range of approximately 1-20 μm of the back surface 100b. Additionally, and as will be discussed in further detail below, after the completion of processing activities above the front side 100f of the wafer 100, such as processing steps to form a metallization system above the contact structure layer 104 and the like, the wafer 100 is thinned from the back side 100b so as to expose the finished TSV's 120 (see FIG. 1f).
FIG. 1c shows a further advanced step of the illustrative prior art method illustrated in FIG. 1b after the patterned resist mask layer 108 has been removed from above the hardmask layer 107. Depending on the overall chip configuration and design considerations, an isolation layer 111 may be formed on or adjacent to the exposed surfaces of the TSV openings 100 so as to eventually electrically isolate the finished TSV's 120 (see FIG. 1f) from the substrate 101, the device layer 102, and/or the contract structure layer 104. As shown in FIG. 1c, the isolation layer 111 may be formed above all exposed surfaces of the wafer 100, including the upper surface 107u of the hardmask layer 107, and the sidewall and bottom surfaces 110s, 110b of the TSV openings 110. It should be noted that, depending on the overall device requirements and processing scheme, an intervening material layer (not shown), such as an adhesion layer or barrier layer, and the like, may be deposited between the isolation layer 111 and the surfaces 110s, 110b. In certain embodiments, the isolation layer 111 may be formed by performing a suitable conformal deposition process 131 designed to deposit an appropriate dielectric insulating material layer having a substantially uniform thickness on the exposed surfaces of the TSV openings 110. It should be noted, however, that the as-deposited thickness of the isolation layer 111 may vary to a greater or lesser degree, depending on the specific location and the orientation of the surface onto which it is deposited, as will be further discussed below.
For example, in some embodiments, the isolation layer 111 may be formed of silicon dioxide, and the deposition process 131 may be any one of several deposition techniques well known in the art, such as low-pressure chemical vapor deposition (LPCVD), sub-atmospheric-pressure chemical vapor deposition (SACVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In certain embodiments, the isolation layer 111 may comprise silicon dioxide, and may be deposited based on tetraethylorthosilicate (TEOS) and O3 (ozone) using LPCVD, SACVD or PECVD processes. Additionally, the minimum required as-deposited thickness of the isolation layer 111 may be established as necessary to ensure that the TSV 120 (see FIG. 1f) is electrically isolated from the surrounding layers of the wafer 100. For example, in order to ensure proper surface coverage and layer functionality, the minimum required thickness of the isolation layer 111 at any point within the TSV openings 110 may be on the order of approximately 100-200 nm, whereas in specific embodiments the minimum thickness may be approximately 150 nm. However, as noted previously, even though a substantially conformal deposition process may be used to form the isolation layer 111, the as-deposited thickness of the isolation layer 111 may vary to a greater or lesser degree, depending on the specific location and orientation of the surface where the isolation layer 111 may be deposited.
For example, the as-deposited thickness of the isolation layer 111 may vary from a thickness 111t above the upper surface 107u of the hardmask layer 107, to a thickness 111U near the upper portion of the TSV sidewall 110s, to a thickness 111L near the lower portion of the TSV sidewall 110s, to a thickness 111b at the bottom surface 110b of the TSV opening 110. Furthermore, depending on the type of deposition process utilized and the coverage efficiency obtained, the as-deposited thicknesses 111t, 111U, 111L and 111b may vary from greatest to least by a factor of 2, 3, 4 or even more. For example, when a 50% coverage efficiency is obtained when depositing the isolation layer 111, the least as-deposited thickness may be approximately 50% of the greatest as-deposited thickness—i.e., varying by a factor of 2. Similarly, when the coverage efficiency is 33%, the greatest and least as-deposited thickness may vary by a factor of approximately 3, and when the coverage efficiency is 25% or less, the as-deposited thicknesses of the isolation layer 111 may vary by a factor of approximately 4 or more.
Table 1 below lists some exemplary as-deposited thicknesses of the isolation layer 111 when deposited using PECVD based on TEOS. The process designations listed in Table 1 are generally indicative of varying process parameters, as well as a targeted nominal thickness in angstroms of the material deposited above the upper surface 107u of the hardmask layer 107. As can be seen from the thickness data presented in Table 1, in order to obtain a minimum as-deposited thickness on the sidewalls 110s of the TSV openings 110 of approximately 150-200 nm, the as-deposited thickness above the upper surface 107u of the hardmask layer 107 may be on the order of approximately 700 nm or more, resulting in a coverage efficiency of around 25-30%. Furthermore, as will be discussed in greater detail below, the substantially increased thickness 111t of the layer 111 above the upper surface 107u of the hardmask layer 107 may, in some instances, result in processing difficulties during subsequently performed CMP steps adapted for planarizing the wafer 100 after deposition of the conductive material used to form the finished TSV's 120 (see FIG. 1f).
TABLE 1As-Deposited Isolation Layer ThicknessesAs-Deposited Thicknesses (nm)Process111t111U111L111b 4k 350140-180  60-120 60 6k 612260-300115-130108 8k 720320-350150-20013016k1600 250-300140-230260
FIG. 1d depicts the illustrative prior art method of FIG. 1c after a barrier layer 112 has been formed above the wafer 100. In some embodiments, the barrier layer 112 may serve to prevent the conductive material comprising the finished TSV's 120 (see FIG. 1f) from diffusing into and/or through the isolation layer 111, or into and/or through the ILD layer 104a, a situation that could significantly affect the overall performance of the circuit elements 103, the contact vias 105, and/or the conductive lines 106. Furthermore, the barrier layer 112 may also act as an adhesion layer, thereby potentially enhancing that overall bond between the contact material of the finished TSV's 120 and the underlying dielectric isolation layer 111.
As shown in FIG. 1d, the barrier layer 112 may be formed above all exposed surfaces of the isolation layer 111, including the exposed surfaces inside of the TSV openings 110. In certain illustrative embodiments, the barrier layer 112 may be deposited above the isolation layer 111 by performing a substantially conformal deposition process 132, such as CVD, PVD, ALD (atomic layer deposition) and the like. Depending on device requirements and TSV design parameters, the barrier layer 112 may comprise any one of a number of suitable barrier layer materials well known in the art to reduce and/or resist the diffusion of metal into a surrounding dielectric, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), and the like. Furthermore, due to the relatively large width 110w of the TSV openings 110 as compared to a contact via used to form an electrical interconnection to a typical integrated circuit element—such as the contact vias 105—the thickness of the barrier layer 112 may not be critical to the overall performance characteristics of the TSV's 120 (see FIG. 1f). Accordingly, the thickness of the barrier layer 112 may in some illustrative embodiments range between 40 nm and 200 nm, depending on the material type and deposition method used to form the barrier layer 112, whereas in specific embodiments, the thickness of the barrier layer 112 may range from 50-100 nm.
After the barrier layer 112 has been formed above the exposed surfaces of the isolation layer 111, a layer of conductive contact material 113 may then be formed above the wafer 100 so as to completely fill the TSV openings 110, as shown in FIG. 1e. Depending on the TSV design requirements, the layer of conductive contact material 113 may be substantially comprised of a conductive metal such copper, and the like, or in certain embodiments may comprise a suitable copper metal alloy. In some embodiments, the TSV openings 110 may be filled with the layer of conductive contact material 113 based on a substantially “bottom-up” deposition process 133 well known to those skilled in the art, such as a suitably designed electrochemical plating (ECP) process and the like, thereby reducing the likelihood that voids may be formed and/or trapped in the finished TSV's 120 (see FIG. 1f). In other illustrative embodiments, an electroless plating process may be employed. Additionally, and depending on the type of material used for the barrier layer 112 and the type of deposition process 133 used to fill the TSV openings 110, a seed layer (not shown) may be formed on the barrier layer 112 prior to performing the deposition process 133. In certain embodiments, the optional seed layer may be deposited using a highly conformal deposition process, such as sputter deposition, ALD, and the like, and may have a thickness ranging from approximately 5-10 nm. However, in other illustrative embodiments, the thickness of the barrier layer 133 may be even greater—for example, from 10-15 nm—whereas in still other embodiments, the thickness may be even less—for example, from 1-5 nm. Depending on the processing requirements, still other barrier layer thicknesses may be used.
It should be noted that, as a result of the “bottom-up” deposition process 133 used to fill the TSV openings 110 in some prior art processes, depressions 114 may sometimes be present in the layer of conductive contact material 113 above each of the TSV openings 110 after completion of the deposition process 133. Depending on the depth 114a of any depressions 114 that may be present, a significant amount of material “overburden” 113b, or additional thickness, may need to be deposited outside of the TSV openings 110 and above the upper horizontal surfaces 100s of the wafer 100 to ensure that the TSV openings 110 are completely filled with the layer of conductive contact material 113. In order to ensure that the depth 114a of the depressions 114 in the conductive contact material layer 113 does not encroach into the TSV openings 110, the overburden 113b may need to at least equal, if not exceed, the depth 114a. Depending on the width 110w, depth 110d, and aspect ratio of the TSV openings 110, the overburden 113b may, in some illustrative embodiments, be greater than 2 nm, and may range as high as 4-5 μm, or even greater. However, it should be noted that when such a large conductive contact layer overburden thickness is necessary in order to ensure complete filling of the TSV openings 110, the effectiveness of any subsequently performed planarization processes, such as CMP processes and the like, can be severely impacted. Moreover, when considered in conjunction with the increased thickness 211t of the isolation layer 211 above the upper surface 207u of the hardmask layer 207, the effectiveness of a planarization process may be further impacted, as will be discussed in more detail below.
In those process recipes wherein the layer of conductive contact material 113 comprises an electroplated copper and/or copper alloy, the wafer 100 shown in FIG. 1e may be exposed to a heat treatment process after the layer of conductive contact material 113 has been formed, so as to facilitate grain growth and stabilization of the copper film characteristics. For example, the heat treatment process may be an annealing process performed under atmospheric pressure conditions at a temperature ranging between 100° C. and 300° C., and for a time of 1 hour or less. Depending on the overall integration scheme and thermal budget of the wafer 100, other heat treatment recipes may also be employed.
FIG. 1f shows the illustrative prior art process depicted in FIG. 1e in a further advanced manufacturing stage. As shown in FIG. 1f, a planarization process 140, such as a CMP process and the like, may be performed to remove the horizontal portion of the layer of conductive contact material 113 formed outside of the TSV openings 110 from above the wafer 100. Furthermore, in some embodiments the horizontal portions of the isolation layer 111 formed above the wafer 100 and outside of the TSV openings 110 may also be removed during the planarization process 140. Moreover, the thickness of the hardmask layer 107, which as noted previously may act as a CMP stop layer, may also be reduced during the planarization process 140. After completion of the planarization process 140, additional processing of the front side 100f of the wafer 100 may be performed, such as forming metallization layers and the like above the TSV's 120 and the contact structure layer 104. Thereafter, the wafer 100 may be thinned from the back side 100b so as to reduce the thickness of the substrate 101 (indicated in FIG. 1f by dashed line 101t) and expose the bottom surfaces 120b of the TSV's 120 in preparation for wafer stacking and substrate bonding—i.e., 3D integrated circuit assembly.
As noted previously, the increased thicknesses of the isolation layer 111 and the layer of conductive contact material 113 having large amount of overburden 113b formed outside of the TSV openings 110 and above the upper surface 107u of the hardmask layer 107 may substantially impact the overall effectiveness of the planarization process 140. For example, during the initial stages of the planarization process 140, when the material being planarized may only be the conductive contact material 113, the planarization process 140 may be performed using parameters that are substantially selective to the composition of the conductive contact material 113, which may be, for example, copper or a copper alloy. Furthermore, considering that a large amount of overburden 113b may be deposited so as to ensure that the TSV openings 110 are completely filled, the parameters of the planarization process 140 may be adjusted so as to shorten the duration of the planarizing step, thereby resulting in a significant and aggressive removal of material. For example, an aggressive slurry chemistry that is highly selective to the material comprising the conductive contact material 113, such as copper, may be used during the initial stage of the planarization process 140 so as to reduce overall processing time. However, once the barrier layer 112 and/or isolation layer 111 is encountered during the planarization process 140, the aggressive parameters used to selectively planarize the conductive contact material 113 may be adjusted so that multiple materials having different planarizing characteristics—i.e., the conductive contact material 113, the barrier layer 112, and the isolation layer 111—may be planarized simultaneously. Accordingly, the slurry chemistry may be changed to a chemistry that is selective to, for example, the material comprising the barrier layer 112, but that is less selective to the other types of materials that may be encountered during this stage of the planarization process 140. In general, however, it should be noted that planarization will typically proceed at a significantly slower pace during this stage of the planarization process 140 than during the initial aggressive stage noted above, and as will be discussed in detail below.
It should be appreciated that the removal rates of the different materials exposed to the planarization process 140 during this stage of processing the wafer 100 may not be the same, or in some instances, may not even be similar. For example, the removal rate of materials such as copper and/or copper alloys and the like (which may comprise the conductive contact material 113), may be significantly lower than the removal rate of dielectric materials such silicon dioxide and the like (which may comprise the isolation layer 111) when both are exposed to a planarization process 140 based on a slurry chemistry that is selective to the material of the barrier layer 112 as described above. As such, the material of the isolation layer 111 may be planarized more quickly than the material of the layer of conductive contact material 113, thereby resulting in a substantially non-planar protruding region 115 above each finished TSV 120, as shown in FIG. 1f. In some embodiments, the height 115a of the protruding region 115 may exceed 100 nm or more, and under certain conditions—such as, for example, the presence and/or depth 114a of a depression 114, the specific CMP process recipe employed, the material removal rate differential, and the like—the height 115a may be as large as 300-500 nm, or even greater. Furthermore, the presence of the protruding region 115 in the finished TSV's 120 may translate into additional defects in the layers of a metallization system (not shown) subsequently formed above the TSV's 120 and the contact structure layer 104, such as voids, gaps, and/or additional protruding, non-planar regions, thereby potentially leading to decreased product yield and reduced product performance.
Accordingly, there is a need to implement new design strategies to address the manufacturing and performance issues associated with the typical methods used for forming TSV's. The present disclosure relates to methods for avoiding, or at least reducing, the effects of one or more of the problems identified above.